1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device suitable for the formation of a wiring layer.
2. Description of the Related Art
Recently, with a request for miniaturization, a damascene method is often adopted in manufacturing a semiconductor device. Moreover, in the damascene method, in terms of CMP (Chemical Mechanical Polishing) of a wiring material and photolithography technology, three-layer structured hard mask is sometimes used when a via hole and a wiring trench are formed in an interlayer insulating film. This is for the following reason.
FIG. 4A to FIG. 4C are sectional views showing the progress of CMP in the damascene method step by step. When a porous silica film 114 as an interlayer insulating film is formed and a wiring trench is formed in this porous silica film 114, an insulating film 115 which prevents the porous silica film 114 from being polished and an insulating film 116 as a polishing allowance in CMP are needed. In order to perform CMP with high precision, that is, in order to enable the thickness of each film to be a designed value, the insulating film 115 is required to have high hardness, and the insulating film 116 is required to be polished by CMP more easily than the insulating film 115. Hence, a SiC film, a SiN film, a SiOC film with high hardness, or the like is used as the insulating film 115, and an SiO2 film or the like is used as the insulating film 116. By using these films, when CMP is performed as shown in FIG. 4B after a Cu film 117 is embedded in the wiring trench as shown in FIG. 4A, the CMP is stopped at the surface of the insulating film 115 as shown in FIG. 4C.
When the SiO2 film is used as the insulating film 116, a selection ratio between the insulating film 116 and the porous silica film is low. Therefore, the insulating film 116 needs to be relatively thick. However, in the case of such a two-layer structured hard mask as shown in FIG. 4A to FIG. 4C, it is impossible to thicken the insulating film 116. This is for the following reason.
FIG. 5A and FIG. 5B are sectional views showing the progress of etching with an ArF resist step by step. For example, as shown in FIG. 5A, an antireflection film 120 such as an BARC (Bottom Anti-Reflection Coating) is formed on a film to be processed 119 such as the insulating film 116, and a resist mask 121 made of the ArF resist is formed on the antireflection film 120. Then, the antireflection film 120 and the film to be processed 119 are etched with the resist mask 121 as a mask. Since the ArF resist has low resistance to etching at this time and thereby the resist mask 121 becomes thinner, the processable depth of the film to be processed 119 is shallow. Further, recently, with a request for miniaturization, it becomes necessary to reduce the thickness of the resist mask 121 in order to improve resolution. Hence, the depth of the film to be processed 119 which can be processed with the resist mask 121 becomes shallower.
In these circumstances, it is impossible to thicken the insulating film 116 in the case of the two-layer structured hard mask. Hence, a three-layer structured hard mask is used by further forming a thin hard mask on the insulating film 116.
Prior arts are disclosed in Japanese Patent Laid-open No. 2000-351976, Japanese Patent Laid-open No. 2001-77196, and Japanese Patent Laid-open No. 2002-222860.
However, it has become difficult to cope with further miniaturization even if the three-layer structured hard mask is used. FIG. 6A to FIG. 6D are sectional views showing a method for manufacturing a semiconductor device, which adopts a conventional damascene method, step by step.
In the conventional manufacturing method, as shown in FIG. 6A, a SiC film 103, a porous silica film 104, a SiC film 105, a SiO2 film 106, a SiN film 107, and an antireflection film 109 such as an BARC are formed in sequence on a Cu wiring 102, and thereafter a resist mask 110 made of an ArF resist is formed.
Then, as shown in FIG. 6B, the antireflection film 109 and the SiN film 107 are etched with the resist mask 110 as a mask. Subsequently, the resist mask 110 is removed by ashing.
Thereafter, as shown in FIG. 6C, the SiO2 film 106 is etched with the SiN film 107 as a mask. Then, the SiC film 105 is etched with the SiO2 film 106 as a mask, and simultaneously the SiN film 107 is removed.
Subsequently, as shown in FIG. 6D, the porous silica film 104 and the SiC film 103 are etched with the SiO2 film 106 as a mask. Thereafter, a wiring is formed.
In the aforementioned conventional manufacturing method, as shown in FIG. 6D, a selection ratio between the SiO2 film 106 and the inorganic porous silica film 104 is low, whereby an end portion of the SiO2 film 106 used as the hard mask is rounded off. As a result, the size of an opening becomes larger than a designed value, which easily causes leakage between adjacent wirings.
To avoid the aforementioned drawback, it is conceivable to thicken the SiO2 film 106, but to thicken the SiO2 film 106, it is also necessary to thicken the SiN film 107 used as a hard mask when the SiO2 film 106 is patterned, which causes a problem regarding photolithography.
If the SiN film 107 is thickened, the following problem arises. FIG. 7A to FIG. 7C are sectional views showing a method for forming a resist mask by a dual damascene method step by step.
In a trench-first exposure type dual damascene method, as shown in FIG. 7A, a hard mask 123 on which a wiring trench pattern is formed is formed on a film to be processed 122, and thereafter, as shown in FIG. 7B, a resist mask 124 made of an ArF resist is formed on the entire surface. At this time, the resist mask 124 in a portion on which a wide wiring trench pattern is formed is thinner than that in other portions. Then, when a via hole pattern is formed on the resist mask 124 by exposure and developing as shown in FIG. 7C, the size of the via hole becomes larger than a designed value in the portion where the resist mask 124 is thinner.
Moreover, as described above, to improve the resolution, it is necessary to reduce the thickness of the resist mask, whereby the top-layer hard mask needs to be thin.